1. Field of the Invention
The present invention relates to a ferroelectric memory device, and in particular to an improved cell structure of a ferroelectric memory device which can prevent a data loss.
2. Description of the Background Art
As illustrated in FIG. 1, a conventional ferroelectric memory cell includes a ferroelectric capacitor X0 or X1 operated as a charge storing unit, and a MOS transistor NO or N1 for sense and read operations. Read and write operations are performed by driving a plate line PL. Here, the MOS transistor N0 is turned on according to an enable state of a word line WL0, and the MOS transistor N1 is turned on according to an enable state of a word line WL1.
That is, in the conventional ferroelectric memory cell, as shown in FIG. 2, a bit line precharge signal BLP is maintained at a high H level at an initial stage, and thus MOS transistors N2, N3 are turned on. As a result, a pair of bit lines BL, /BL become a ground voltage level. Thereafter, the bit line precharge signal BLP is transited from high H to low L, and thus the MOS transistors N2, N3 are turned off. Accordingly, the pair of bit lines BL, /BL are precharged to the ground voltage level. As the word line WL0 of the two word lines W0, W1 is selected and enabled at a voltage level of "Vcc+Vt", the MOS transistor N0 is turned on. When the plate line PL is transited from low to high, the bit line BL becomes a high level, and the bit line bar /BL becomes a low level. When the plate line PL become a high level, the bit line BL is increased to a voltage to be compared with a reference voltage, and thus a sense amplifier 14 senses that data "1" is currently stored. Thereafter, when the bit line precharge signal BLP is transited from low to high, the pair of bit lines BL, /BL become the ground voltage level.
In the conventional ferroelectric memory cell, the plate line PL consists of platinum Pt. A dielectric constant of the platinum is great, and thus a parasitic capacitance is also great. Accordingly, as depicted in FIG. 2, until the plate line PL is driven from low to high after the word line WL0 is selected, a predetermined delay time tl is consumed, thereby lowering a speed in reading or writing a data.
As illustrated in FIG. 3, in order to solve the delay time of the circuit, there has been suggested a circuit for removing a time delayed in driving the plate line PL by applying "Vcc/2" to the plate line PL.
That is, the circuit as shown in FIG. 3 further includes MOS transistors N4. N5 connected in series between the pair of bit lines BL, /BL, turned on according to a bit line half Vcc precharge signal BCG, and converting the pair of bit lines BL, /BL to a Vcc/2 state, and applies Vcc/2 to the plate line PL, differently from the circuit as shown in FIG. 1.
In the case of the circuit as shown in FIG. 3, as illustrated in FIG. 4, while the data sensing operation is performed on the selected word line WL0 at a high speed, the bit line half Vcc precharge signal BCG is maintained at a low level. When the data sensing operation is finished on the word line WL0, the bit line half Vcc precharge signal BCG is transited from low to high, thereby turning on the MOS transistors N4, N5. Accordingly, the pair of bit lines BL, /BL become a Vcc/2 state, and the data is restored. Thereafter, when the bit line precharge signal BLP is transited from low to high, the MOS transistors N2, N3 are turned on, and thus the pair of bit lines BL, /BL become the ground voltage level.
However, in the operation of the circuit as shown in FIG. 3, when the selected word line WL0 is transited from high to low, the MOS transistor N0 is turned off. At this time, the Vcc/2 voltage is being applied to the plate line PL, and thus an upper electrode (a portion connected to a source of the MOS transistor N0) of the ferroelectric capacitor X0 is floated. Accordingly, a leakage is generated at the upper electrode of the ferroelectric capacitor X0, and thus the data are lost.